1) Field of the Invention
This invention relates generally to the fabrication of capacitors and more particularly to the fabrication of stacked capacitor arrays for a memory device.
2) Description of the Prior Art
A typical dynamic random access memory (DRAM) cell consists of a single transistor and a storage capacitor. Digital information is stored in the capacitor and accessed through the transistor, by the way of addressing the desired memory cell, which is connected with other such cells through an array of bit lines and word lines. In order to construct high density DRAMs in a reasonably sized chip area, both the transistor and capacitor element must occupy less lateral space in each memory cell.
As DRAMs are scaled down in dimensions, there is a continuous challenge to maintain a sufficiently high stored charge per capacitor unit area. In dynamic semiconductor memory storage devices it is essential that storage node capacitor cell plates be large enough to retain an adequate voltage level in spite of parasitic capacitances and noise that may be present during circuit operation. As is the case for most semiconductor integrated circuitry, circuit density is continuing to increase at a fairy constant rate. The issue of maintaining storage node capacitance is particularly important as the density of DRAM cells continues to increase for future generations of memory devices. The ability to densely pack storage cells while maintaining required storage capability is a crucial requirement of semiconductor manufacturing technologies if future generations of expanded memory array devices are to be successfully manufactured.
Generally, in a 64 MB DRAM having a 1.5 .mu.m.sup.2 memory cell area employing an ordinary two dimensional stacked capacitor cell, sufficient cell capacitance cannot be obtained even though a higher dielectric constant material, e.g., tantalum oxide (Ta.sub.2 0.sub.5), is used. Therefore, stacked capacitors having a three-dimensional structure have been suggested to improve cell capacitance. Such stacked capacitors include, for example double-stacked, fin-structured, cylindrical, spread-stacked, and box structured capacitors. In order to increase the surface area of the capacitor, there have also been proposed methods of forming a capacitor with a pin structure extending throughout a multi-layer structure of the capacitor to connect the layers with one another, and methods of forming a capacitor using a hemispherical grain polysilicon (HSG) process using polysilicon grains.
A problem with current methods of fabricating stacked capacitors is that many photolithographic steps are used. The photo steps add cost and manufacturing complexity. Moreover, photolithographic processes require relatively large image tolerances which make the capacitor larger. To miniaturize the capacitor further processes must be developed with reduce the number of photolithographic steps.
Workers in the art are aware of the density and photolithographic limitation of present capacitors and have attempted to resolve them. U.S. Pat. No. 5,476,806 (Roh), U.S. Pat. No. 5,185,282 (Lee) and U.S. Pat. No. 5,491,103 (Ahn) disclose methods for forming crown type stacked capacitors. However, these methods and structures can be further optimized. Moreover, many of the other prior art methods require substantially more processing steps (especially photo steps) or/and planar structures which make the manufacturing process more complex and costly. Therefore, it is very desirable to develop processes that are as simple as possible and maximize the capacitance per unit area. There is a challenge to develop methods of manufacturing these capacitors that minimize the manufacturing costs and maximize the device yields. In particular, there is a challenge to develop a method which minimizes the number of photoresist operations and provides maximum process tolerance to maximize product yields.